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integrated power solution with quad buck regulators and supervisory preliminary technical data ADP5053 rev. prb document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its us e. specifications subject to change without notice. no license is granted by implication or otherwise unde r any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective owners. one technology way, p.o. box 9106, norwood, ma 0206 29106, u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all ri ghts reserved. technical support www.analog. com features wide input voltage range: 4.5 v to 15.0 v 1.5% output accuracy over full temperature range 250 khz to 1.4 mhz adjustable switching frequency adjustable/fixed output options via factory fuse power regulation channel 1 and channel 2: programmable 1.2 a/2.5 a/4 a sync buck regulators with lowside fet driver channel 3 and channel 4: 1.2 a sync buck regulators single 8 a output (channel 1 and channel 2 operated in parallel) precision enable with 0.8 v accurate threshold active output discharge switch fpwm or automatic pwm/psm selection frequency synchronization input or output optional latchoff protection on ovp/ocp failure powergood flag on selected channels uvlo, ocp, and tsd protection opendrain processor reset with external adjustable threshold monitoring watchdog refresh input manual reset input applications small cell base stations fpga and processor applications security and surveillance medical applications typical application circuit channel 2 buck regulator (4a) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 l2 vreg sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 l3 bst3 sw3 fb3 pgnd3 l4 vreg bst4 sw4 fb4 pgnd4 vreg pvin1 comp1 en1 pvin2 comp2 en2 pvin3 ss34 comp3 en3 pvin4 comp4 en4 c2 c1 c4 c3 c5 c6 c7 c8 c9 c10 c11 c12 c13 4.5v to 15v vout1 vout2 vout3 vout4 voutx r ilim1 r ilim2 vreg exposed pad ss12 c0 vdd watchdog and reset vth wdi mr rsto ADP5053 channel 1 buck regulator (4a) channel 4 buck regulator (1.2a) 11636-001 figure 1. general description the ADP5053 combines four high performance buck regulators, supervisory, watchdog, and manual reset in a 48lead lfcsp package that meets demanding performance and board space requirements. the device enables direct connection to high input voltages up to 15.0 v with no preregulators. channel 1 and channel 2 integrate highside power m osfet and lowside mosfet drivers. external nfets can be used in lowside power devices to achieve an efficiency optimized so lution and deliver a programmable output current of 1.2 a, 2.5 a, or 4 a. combining channel 1 and channel 2 in a parallel con figuration can provide a single output with up to 8 a of curre nt. channel 3 and channel 4 integrate both highside an d lowside mosfets to deliver an output current of 1.2 a. the switching frequency of the ADP5053 can be programmed or synchronized to an external clock. the ADP5053 contains a precision enable pin on each channel for easy power up sequencing or adjustable uvlo threshold. the ADP5053 contains supervisory circuits that monitor voltage level. the watchdog timer can generate a reset if t he wdi is not toggled within a preset timeout period. processor r eset mode or system power on/off switch mode can be selected for manual reset functionality. table 1. family models model channels i 2 c package adp5050 four buck, one ldo yes 48lead lfcsp adp5051 four buck, supervisory yes 48lead lfcsp adp5052 four buck, one ldo no 48lead lfcsp ADP5053 four buck, supervisory no 48lead lfcsp
ADP5053 preliminary technical data rev. prb | page 2 of 41 table of contents features .......................................... ................................................... .. 1 applications ...................................... ................................................. 1 typical application circuit ....................... ....................................... 1 general description ............................... ........................................... 1 revision history ........................... error! bookmark not defined. detailed functional block diagram ................. .............................. 3 specifications .................................... ................................................. 4 buck regulator specifications ..................... ................................ 5 supervisory specifications ........................ ................................... 7 absolute maximum ratings .......................... .................................. 8 thermal resistance ................................ ....................................... 8 esd caution ....................................... ........................................... 8 pin configuration and function descriptions ....... ...................... 9 typical performance characteristics ............... ............................. 11 theory of operation ............................... ........................................ 16 buck regulator operational modes .................. ....................... 16 adjustable and fixed output voltages .............. ....................... 16 internal regulators (vreg and vdd) ................ .................... 16 separate supply applications....................... .............................. 17 lowside device selection.......................... ............................... 17 bootstrap circuitry ............................... ...................................... 17 active output discharge switch .................... ........................... 17 precision enabling ................................ ...................................... 17 oscillator ........................................ .............................................. 17 synchronization input/output ...................... ............................ 18 soft start ........................................ ............................................... 18 parallel operation ................................ ....................................... 19 startup with precharged output .................... ........................... 19 current limit protection .......................... ................................. 20 frequency foldback ................................ .................................... 20 hiccup protection ................................. ...................................... 20 latchoff protection............................... .................................... 20 undervoltage lockout (uvlo) ....................... ......................... 21 powergood function ............................... ................................. 21 thermal shutdown .................................. ................................... 21 supervisory ....................................... ........................................... 21 applications information .......................... ..................................... 24 adisimpower design tool ........................... ............................. 24 programming the adjustable output voltage ......... ................ 24 voltage conversion limitations .................... ........................... 24 current limit setting ............................. .................................... 24 soft start setting ................................ ......................................... 25 inductor selection ................................ ....................................... 25 output capacitor selection ........................ ............................... 25 input capacitor selection ......................... ................................. 26 lowside power device selection ................... ......................... 26 programming the uvlo input ........................ ........................ 26 compensation components design .................... .................... 27 power dissipation ................................. ...................................... 27 junction temperature .............................. ................................... 28 design example .................................... ........................................... 30 setting the switching frequency ................... ........................... 30 setting the output voltage ........................ ................................ 30 setting the current limit ......................... .................................. 30 selecting the inductor ............................ .................................... 30 selecting the output capacitor .................... ............................. 31 selecting the lowside mosfet ..................... ........................ 31 designing the compensation network ................ ................... 31 selecting the soft start time ..................... ................................ 31 selecting the input capacitor ..................... ............................... 31 recommended external components ................... .................. 32 circuit board layout recommendations .............. ...................... 34 typical application circuits ...................... .................................... 35 factory programmable options ...................... ............................. 38 factory default options ........................... ................................. 39 outline dimensions................................. ....................................... 40 ordering guide .................................... ....................................... 40
preliminary technical data ADP5053 rev. prb | page 3 of 41 detailed functional block diagram q1 q dg1 uvlo1 pvin1 sw1 bst1 vreg vreg driver driver pgnd dl1 control logic and mosfet driver with anticross protection control logic and mosfet driver with anticross protection en1 0.8v 1m hiccup and latch-off ocp comp1 fb1 0.8v clk1 slope comp clk1 0.72v pwrgd1 zero cross current-limit selection frequency foldback + ? + ? + ? ? + + ? + ? + ? channel 1 buck regulator duplicate channel 1 channel 2 buck regulator current balance en2 comp2 fb2 dl2 pvin2 sw2 bst2 vid1 0.88v ovp latch-off ea1 cmp1 rt oscillator sync/mode soft start decoder ss12 ss34 vdd vreg internal regulator pvin1 vreg pwrgd int housekeeping logic uvlo3 pvin3 sw3 bst3 vreg vreg driver q3 q4 driver pgnd3 en3 comp3 fb3 channel 3 buck regulator duplicate channel 3 channel 4 buck regulator en4 comp4 fb4 pgnd4 pvin4 sw4 bst4 a cs1 + ? + ? a cs3 wdi reset generator 0.5v supervisory 0.8v 1m hiccup and latch-off ocp 0.8v clk3 slope comp clk3 0.72v pwrgd3 frequency foldback + ? + ? + ? ? + + ? + ? vid3 0.88v ovp latch-off ea3 cmp3 zero cross vth debounce watchdog detector 11636-002 mr rsto figure 2. detailed functional block diagram
ADP5053 preliminary technical data rev. prb | page 4 of 41 specifications v in = 12 v, v vreg = 5.1 v, t j = ?40c to +125c for minimum and maximum specications , and t a = 25c for typical specifications, unless otherwise noted. table 2. parameter symbol min typ max unit test conditions/c omments input supply voltage range v in 4.5 15.0 v pvin1, pvin2, pvin3, pvin4 pins quiescent current pvin1, pvin2, pvin3, pvin4 p ins operating quiescent current i q 4.8 6.35 ma no switching, all enx pins high i shdn 25 65 a all enx pins low undervoltage lockout uvlo pvin1, pvin2, pvin3, pvin4 pins threshold rising v uvlorising 4.2 4.36 v falling v uvlofalling 3.6 3.78 v hysteresis v hys 0.42 v oscillator circuit switching frequency f sw 700 740 780 khz rt = 25.5 k range 250 1400 khz sync input input clock range f sync 250 1400 khz input clock pulse width minimum on time t sync_min_on 100 ns minimum off time t sync_min_off 100 ns input clock high voltage v h (sync) 1.3 v input clock low voltage v l (sync) 0.4 v sync output clock frequency f clk f sw khz positive pulse duty cycle t clk_pulse_duty 50 % rise or fall time t clk_rise_fall 10 ns high level voltage v h (sync_out) v vreg v precision enabling en1, en2, en3, en4 pins high level threshold v th_h (en) 0.806 0.832 v low level threshold v th_l (en) 0.688 0.725 v pulldown resistor r pulldown (en) 1.0 m power good internal powergood rising threshold v pwrgd (rise) 86.3 90.5 95 % hysteresis v pwrgd (hys) 3.3 % falling delay t pwrgd_fall 50 s rising delay for pwrgd pin t pwrgd_pin_rise 1 ms leakage current for pwrgd pin i pwrgd_leakage 0.1 1 a output low voltage for pwrgd pin v pwrgd_low 50 100 mv i pwrgd = 1 ma internal regulators vdd output voltage v vdd 3.2 3.305 3.4 v i vdd = 10 ma current limit i lim_vdd 20 51 80 ma vreg output voltage v vreg 4.9 5.1 5.3 v dropout voltage v dropout 225 mv i vreg = 50 ma current limit i lim_vreg 50 95 140 ma thermal shutdown
preliminary technical data ADP5053 rev. prb | page 5 of 41 parameter symbol min typ max unit test conditions/c omments threshold t shdn 150 c hysteresis t hys 15 c buck regulator specifications v in = 12 v, v vreg = 5.1 v, f sw = 600 khz for all channels, t j = ?40c to +125c for minimum and maximum specication s, and t a = 25c for typical specifications, unless otherwise noted. table 3. parameter symbol min typ max unit test conditions/c omments channel 1 sync buck regulator fb1 pin fixed output options v out1 0.85 1.60 v fuse trim adjustable feedback voltage v fb1 0.800 v feedback voltage accuracy v fb1 (default) ?0.55 +0.55 % t j = 25c ?1.25 +1.0 % 0c t j 85c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb1 0.1 a adjustable voltage sw1 pin highside power fet on resistance r dson (1h) 100 m pintopin measurement current limit threshold i th (ilim1) 3.50 4.4 5.28 a r ilim1 = floating 1.91 2.63 3.08 a r ilim1 = 47 k 4.95 6.44 7.48 a r ilim1 = 22 k minimum on time t min_on1 117 155 ns f sw = 250 khz to 1.4 mhz minimum off time t min_off1 1/9 t sw ns f sw = 250 khz to 1.4 mhz lowside driver, dl1 pin rising time t rising1 20 ns c iss = 1.2 nf falling time t falling1 3.4 ns c iss = 1.2 nf sourcing resistor t sourcing1 10 sinking resistor t sinking1 0.95 error amplifier (ea), comp1 pin ea transconductance g m1 310 470 620 s soft start soft start time t ss1 2.0 ms ss12 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup1 7 t ss1 ms c out discharge switch on resistance r dis1 250 channel 2 sync buck regulator fb2 pin fixed output options v out2 3.3 5.0 v fuse trim adjustable feedback voltage v fb2 0.800 v feedback voltage accuracy v fb2 (default) ?0.55 +0.55 % t j = 25c ?1.25 +1.0 % 0c t j 85c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb2 0.1 a adjustable voltage sw2 pin highside power fet on resistance r dson (2h) 110 m pintopin measurement current limit threshold i th (ilim2) 3.50 4.4 5.28 a r ilim2 = floating 1.91 2.63 3.08 a r ilim2 = 47 k 4.95 6.44 7.48 a r ilim2 = 22 k minimum on time t min_on2 117 155 ns f sw = 250 khz to 1.4 mhz minimum off time t min_off2 1/9 t sw ns f sw = 250 khz to 1.4 mhz
ADP5053 preliminary technical data rev. prb | page 6 of 41 parameter symbol min typ max unit test conditions/c omments lowside driver, dl2 pin rising time t rising2 20 ns c iss = 1.2 nf falling time t falling2 3.4 ns c iss = 1.2 nf sourcing resistor t sourcing2 10 sinking resistor t sinking2 0.95 error amplifier (ea), comp2 pin ea transconductance g m2 310 470 620 s soft start soft start time t ss2 2.0 ms ss12 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup2 7 t ss2 ms c out discharge switch on resistance r dis2 250 channel 3 sync buck regulator fb3 pin fixed output options v out3 1.20 1.80 v fuse trim adjustable feedback voltage v fb3 0.800 v feedback voltage accuracy v fb3 (default) ?0.55 +0.55 % t j = 25c ?1.25 +1.0 % 0c t j 85c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb3 0.1 a adjustable voltage sw3 pin highside power fet on resistance r dson (3h) 225 m pintopin measurement lowside power fet on resistance r dson (3l) 150 m pintopin measurement current limit threshold i th (ilim3) 1.7 2.2 2.55 a minimum on time t min_on3 90 120 ns f sw = 250 khz to 1.4 mhz minimum off time t min_off3 1/9 t sw ns f sw = 250 khz to 1.4 mhz error amplifier (ea), comp3 pin ea transconductance g m3 310 470 620 s soft start soft start time t ss3 2.0 ms ss34 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup3 7 t ss3 ms c out discharge switch on resistance r dis3 250 channel 4 sync buck regulator fb4 pin fixed output options v out4 2.5 5.5 v fuse trim adjustable feedback voltage v fb4 0.800 v feedback voltage accuracy v fb4 (default) ?0.55 +0.55 % t j = 25c ?1.25 +1.0 % 0c t j 85c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb4 0.1 a sw4 pin highside power fet on resistance r dson (4h) 225 m pintopin measurement lowside power fet on resistance r dson (4l) 150 m pintopin measurement current limit threshold i th (ilim4) 1.7 2.2 2.55 a minimum on time t min_on4 90 120 ns f sw = 250 khz to 1.4 mhz minimum off time t min_off4 1/9 t sw ns f sw = 250 khz to 1.4 mhz error amplifier (ea), comp4 pin ea transconductance g m4 310 470 620 s soft start
preliminary technical data ADP5053 rev. prb | page 7 of 41 parameter symbol min typ max unit test conditions/c omments soft start time t ss4 2.0 ms ss34 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup4 7 t ss4 ms c out discharge switch on resistance r dis4 250 supervisory specifications v in = 12 v, v vreg = 5.1 v; t j = ?40c to +125c for minimum and maximum specications , and t a = 25c for typical specifications, unless otherwise noted. table 4. parameter min typ max unit test conditions/comments threshold voltage (v th ) 0.494 0.500 0.505 v reset timeout period (t rp ) option 0 1.05 1.4 1.97 ms option 1 21 28 38 ms option 2 160 200 260 ms option 3 1.15 1.6 2.17 sec vcc to reset delay (t rd ) 80 s vth falling at 1 mv/s watchdog input watchdog timeout period (t wd ) option 0 4.8 6.3 8 ms option 1 79 102 135 ms option 2 1.14 1.6 2.15 sec option 3 25.6 sec wdi pulse width 80 ns wdi input threshold 0.4 1.2 v wdi input current (source) 8.5 14 18.5 a v wdi = v cc , time average wdi input current (sink) ?15 ?22 ?30 a v wdi = 0 v, time average manual reset input mr input pulse width 1 s mr glitch rejection 280 ns mr pullup resistance 32 55 80 k mr to reset delay 310 ns
ADP5053 preliminary technical data rev. prb | page 8 of 41 absolute maximum ratings table 5. parameter rating pvin1 to pgnd ?0.3 v to +18 v pvin2 to pgnd ?0.3 v to +18 v pvin3 to pgnd3 ?0.3 v to +18 v pvin4 to pgnd4 ?0.3 v to +18 v sw1 to pgnd ?0.3 v to +18 v sw2 to pgnd ?0.3 v to +18 v sw3 to pgnd3 ?0.3 v to +18 v sw4 to pgnd4 ?0.3 v to +18 v pgnd to gnd ?0.3 v to +0.3 v pgnd3 to gnd ?0.3 v to +0.3 v pgnd4 to gnd ?0.3 v to +0.3 v bst1 to sw1 ?0.3 v to +6.5 v bst2 to sw2 ?0.3 v to +6.5 v bst3 to sw3 ?0.3 v to +6.5 v bst4 to sw4 ?0.3 v to +6.5 v dl1 to pgnd ?0.3 v to +6.5 v dl2 to pgnd ?0.3 v to +6.5 v ss12, ss34 to gnd ?0.3 v to +6.5 v en1, en2, en3, en4 to gnd ?0.3 v to +6.5 v vreg to gnd ?0.3 v to +6.5 v sync/mode to gnd ?0.3 v to +6.5 v wdi, rsto , vth to gnd ?0.3 v to +6.5 v mr to gnd ?0.3 v to +3.6 v rt to gnd ?0.3 v to +3.6 v pwrgd to gnd ?0.3 v to +6.5 v fb1, fb2, fb3, fb4 to gnd 1 ?0.3 v to +3.6 v fb2 to gnd 2 ?0.3 v to +6.5 v fb4 to gnd 2 ?0.3 v to +7 v comp1, comp2, comp3, comp4 to gnd ?0.3 v to +3.6 v vdd to gnd ?0.3 v to +3.6 v storage temperate range ?65c to +150c operational junction temperature range ?40c to +12 5c 1 this rating applies to the adjustable output volta ge models of the ADP5053 . 2 this rating applies to the fixed output voltage mo dels of the ADP5053 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera tional section of this specification is not implied. expos ure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worstcase conditions, that i s, a device soldered in a circuit board for surfacemount packa ges. table 6. thermal resistance package type ja jc unit 48lead lfcsp 27.87 2.99 c/w esd caution
preliminary technical data ADP5053 rev. prb | page 9 of 41 pin configuration and function descriptions 12 3 pvin1 pvin1 sw1 4 sw1 5 bst1 6 dl1 7 pgnd 2 4 p v i n 2 2 3 e n 2 2 2 c o m p 2 2 1 f b 2 2 0 p w r g d 1 9 g n d 1 8 g n d 1 7 g n d 1 6 f b 4 1 5 c o m p 4 1 4 e n 4 1 3 g n d 4 4 v r e g 4 5 f b 3 4 6 c o m p 3 4 7 s s 3 4 4 8 e n 3 4 3 s y n c / m o d e 4 2 v d d 4 1 r t 4 0 f b 1 3 9 c o m p 1 3 8 s s 1 2 3 7 e n 1 top view (not to scale) ADP5053 25 bst4 26 pgnd4 27 sw4 28 pvin4 29 30 31 vth 32 wdi 33 pvin3 34 sw3 35 pgnd3 36 bst3 notes 1. the exposed pad must be connected and soldered to an external ground plane. 8 dl2 9 bst2 10 sw2 11 sw2 12 pvin2 11636-003 mr rsto figure 3. pin configuration table 7. pin function descriptions pin no. mnemonic description 1 bst3 highside fet driver power supply for channe l 3. 2 pgnd3 power ground for channel 3. 3 sw3 switching node output for channel 3. 4 pvin3 power input for channel 3. connect a bypass capacitor between this pin and ground. 5 wdi watchdog refresh input from processor. 6 vth monitoring voltage threshold programming. 7 mr manual reset input, active low. 8 rsto opendrain reset output, active low. 9 pvin4 power input for channel 4. connect a bypass capacitor between this pin and ground. 10 sw4 switching node output for channel 4. 11 pgnd4 power ground for channel 4. 12 bst4 highside fet driver power supply for chann el 4. 13 gnd this pin is for internal test purposes. conn ect this pin to ground. 14 en4 enable input for channel 4. an external resi stor divider can be used to set the turnon thresho ld. 15 comp4 error amplifier output for channel 4. conn ect an rc network from this pin to ground. 16 fb4 feedback sensing input for channel 4. 17, 18, 19 gnd these pins are for internal test pur poses. connect these pins to ground. 20 pwrgd powergood signal output. this opendrain output is the powergood signal for the selected ch annels. 21 fb2 feedback sensing input for channel 2. 22 comp2 error amplifier output for channel 2. conn ect an rc network from this pin to ground. 23 en2 enable input for channel 2. an external resi stor divider can be used to set the turnon thresho ld. 24, 25 pvin2 power input for channel 2. connect a b ypass capacitor between this pin and ground. 26, 27 sw2 switching node output for channel 2. 28 bst2 highside fet driver power supply for chann el 2. 29 dl2 lowside fet gate driver for channel 2. conn ect a resistor from this pin to ground to program t he current limit threshold for channel 2. 30 pgnd power ground for channel 1 and channel 2.
ADP5053 preliminary technical data rev. prb | page 10 of 41 pin no. mnemonic description 31 dl1 lowside fet gate driver for channel 1. conn ect a resistor from this pin to ground to program t he current limit threshold for channel 1. 32 bst1 highside fet driver power supply for chann el 1. 33, 34 sw1 switching node output for channel 1. 35, 36 pvin1 power input for the internal 5.1 v vre g linear regulator and the channel 1 buck regulator . connect a bypass capacitor between this pin and ground. 37 en1 enable input for channel 1. an external resi stor divider can be used to set the turnon thresho ld. 38 ss12 connect a resistor divider from this pin to vreg and ground to configure the soft start time f or channel 1 and channel 2 (see the soft start section). this pin is also used to configure parallel operation of chann el 1 and channel 2 (see the parallel operation section). 39 comp1 error amplifier output for channel 1. conn ect an rc network from this pin to ground. 40 fb1 feedback sensing input for channel 1. 41 rt connect a resistor from rt to ground to progr am the switching frequency from 250 khz to 1.4 mhz. for more information, see the oscillator section. 42 vdd output of the internal 3.3 v linear regulato r. connect a 1 f ceramic capacitor between this pi n and ground. 43 sync/mode synchronization input/output (sync). t o synchronize the switching frequency of the part t o an external clock, connect this pin to an external clock with a freque ncy from 250 khz to 1.4 mhz. this pin can also be c onfigured as a synchronization output by factory fuse. forced pwm or automatic pwm/psm selection pin (mo de). when this pin is logic high, the part operates in forced pwm (fpwm) mode. when this pin is logic low, the part operates in automatic pwm/psm mode. 44 vreg output of the internal 5.1 v linear regulat or. connect a 1 f ceramic capacitor between this p in and ground. 45 fb3 feedback sensing input for channel 3. 46 comp3 error amplifier output for channel 3. conn ect an rc network from this pin to ground. 47 ss34 connect a resistor divider from this pin to vreg and ground to configure the soft start time f or channel 3 and channel 4 (see the soft start section). 48 en3 enable input for channel 3. an external resi stor divider can be used to set the turnon thresho ld. 0 epad exposed pad (analog ground). the exposed pad must be connected and soldered to an external grou nd plane.
preliminary technical data ADP5053 rev. prb | page 11 of 41 typical performance characteristics 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 efficienc y (%) i out (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5.0v 11636-103 figure 4. channel 1/channel 2 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 efficienc y (%) i out (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v 11636-004 figure 5. channel 1/channel 2 efficiency curve, v in = 5.0 v, f sw = 600 khz, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 efficienc y (%) i out (a) f sw = 1.0mhz f sw = 600khz f sw = 300khz 11636-005 figure 6. channel 1/channel 2 efficiency curve, v in = 12 v, v out = 1.8 v, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 efficienc y (%) i out (a) v out = 1.2v, fpwm v out = 1.2v, auto pwm/psm v out = 1.8v, fpwm v out = 1.8v, auto pwm/psm v out = 3.3v, fpwm v out = 3.3v, auto pwm/psm 11636-006 figure 7. channel 1/channel 2 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm and automatic pwm/psm modes 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficienc y (%) i out (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5.0v 11636-007 figure 8. channel 3/channel 4 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficienc y (%) i out (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v 11636-008 figure 9. channel 3/channel 4 efficiency curve, v in = 5.0 v, f sw = 600 khz, fpwm mode
ADP5053 preliminary technical data rev. prb | page 12 of 41 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficienc y (%) i out (a) f sw = 1.0mhz f sw = 600khz f sw = 300khz 11636-009 figure 10. channel 3/channel 4 efficiency curve, v in = 12 v, v out = 1.8 v, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 2 efficienc y (%) i out (a) v out = 1.2v, fpwm v out = 1.2v, auto pwm/psm v out = 1.8v, fpwm v out = 1.8v, auto pwm/psm v out = 3.3v, fpwm v out = 3.3v, auto pwm/psm 11636-010 figure 11. channel 3/channel 4 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm and automatic pwm/psm modes ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 1 2 3 4 load regul a tion (%) i out (a) 11636-011 figure 12. channel 1 load regulation, v in = 12 v, v out = 3.3 v, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 line regul a tion (%) input voltage (v) 11636-012 figure 13. channel 1 line regulation, v out = 3.3 v, i out = 4 a, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 0.2 0.4 0.6 0.8 1.0 1.2 load regul a tion (%) i out (a) 11636-013 figure 14. channel 3 load regulation, v in = 12 v, v out = 3.3 v, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 line regul a tion (%) input voltage (v) 11636-014 figure 15. channel 3 line regulation, v out = 3.3 v, i out = 1 a, f sw = 600 khz, fpwm mode
preliminary technical data ADP5053 rev. prb | page 13 of 41 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?50 ?20 10 40 70 100 130 feedback vo lt age accurac y (%) temperature (c) 11636-015 figure 16. 0.8 v feedback voltage accuracy vs. temp erature for channel 1, adjustable output model 550 600 650 700 750 800 850 ?50 ?20 10 40 70 100 130 frequenc y (khz) temperature (c) 11636-017 figure 17. frequency vs. temperature, v in = 12 v 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?50 0 25 ?25 50 75 125 100 150 quiescent current (ma) temperature (c) 11636-018 figure 18. quescient current vs. temperature (inclu des pvin1, pvin2, pvin3, and pvin4) 15 25 35 45 55 65 75 shutdown current (a) temperature (c) ?50 0 25 ?25 50 75 125 100 150 v in = 4.5v v in = 7.0v v in = 12v v in = 15v 11636-019 figure 19. shutdown current vs. temperature (en1, e n2, en3, and en4 low) 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 ?50 ?20 10 40 70 100 130 uvlo threshold (v) temperature (c) rising falling 11636-020 figure 20. uvlo threshold vs. temperature 0 1 2 3 4 5 6 7 4 6 8 10 12 14 16 current limit (a) input voltage (v) r ilim = 22k r ilim = open r ilim = 47k 11636-021 figure 21. channel 1/channel 2 current limit vs. in put voltage
ADP5053 preliminary technical data rev. prb | page 14 of 41 0 20 40 60 80 100 120 140 160 180 200 ?50 ?20 10 40 70 100 130 minimum on time (ns) temperature (c) ch1/ch2 ch3/ch4 11636-022 figure 22. minimum on time vs. temperature ch1 5.00v ch2 10.0mv b w m1.00s a ch1 7.40v 2 1 v out sw 11636-028 figure 23. steady state waveform at heavy load, v in = 12 v, v out = 3.3 v, i out = 3 a, f sw = 600 khz, l = 4.7 h, c out = 47 f 2, fpwm mode ch1 5.00v ch2 50.0mv b w m100s a ch1 11.0mv 2 1 v out sw 11636-029 figure 24. steady state waveform at light load, v in = 12 v, v out = 3.3 v, i out = 30 ma, f sw = 600 khz, l = 4.7 h, c out = 47 f 2, automatic pwm/psm mode ch1 50.0mv b w ch4 2.00a m100s a ch1 ?22.0mv 1 4 v out i out 11636-030 figure 25. channel 1/channel 2 load transient, 1 a to 4 a, v in = 12 v, v out = 3.3 v, f sw = 600 khz, l = 2.2 h, c out = 47 f 2 ch3 2.00a b w ch4 2.00a b w ch2 100mv b w m100s a ch2 ?56.0mv 2 4 v out i out2 i out1 11636-031 figure 26. load transient, channel 1/channel 2 para llel output, 0 a to 6 a, v in = 12 v, v out = 3.3 v, f sw = 600 khz, l = 4.7 h, c out = 47 f 4 ch1 500mv b w ch2 5.00v ch3 5.00v b w ch4 2.00a m1.00ms a ch1 650mv 1 3 2 4 v out i out en pwrgd 11636-032 figure 27. channel 1/channel 2 soft start with 4 a resistance load, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2
preliminary technical data ADP5053 rev. prb | page 15 of 41 ch3 1.00v b w ch1 10.0v b w ch4 1.00a b w ch2 5.00v b w m400s a ch2 2.80v 1 4 2 3 v in v out en i out 11636-033 figure 28. startup with precharged output, v in = 12 v, v out = 3.3 v ch3 5.00v b w ch1 500mv b w ch4 5.00a b w ch2 5.00v b w m10.0ms a ch1 650mv 1 4 2 3 v out i out en pwrgd 11636-034 figure 29. channel 1/channel 2 shutdown with active output discharge, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2 11636-135 ch1 500mv b w ch4 5.00a ch2 10.00v b w m10.0ms a ch1 970mv 1 4 2 v out i out sw figure 30. short-circuit protection entry, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2 11636-136 ch1 500mv b w ch4 5.00a b w ch2 10.0v b w m10.0ms a ch1 970mv 1 4 2 v out i out sw figure 31. short-circuit protection recovery, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2
ADP5053 preliminary technical data rev. prb | page 16 of 41 theory of operation the ADP5053 is a micropower management unit that combines four high performance buck regulators in a 48lead lfcsp package to meet demanding performance and board space requi rements. the device enables direct connection to high input voltages up to 15.0 v with no preregulators to make applications simpler and more efficient. buck regulator operational modes pulse-width modulation (pwm) mode in pwm mode, the buck regulators in the ADP5053 operate at a fixed frequency; this frequency is set by an intern al oscillator that is programmed by the rt pin. at the start of each o scillator cycle, the highside mosfet turns on and sends a positive voltage across the inductor. the inductor current increases until the current sense signal exceeds the peak inductor curr ent threshold that turns off the highside mosfet; this threshold is set by the error amplifier output. during the highside mosfet off time, the inductor current decreases through the lowside mosfet until the nex t oscillator clock pulse starts a new cycle. the buck regulators in the ADP5053 regulate the output voltage by adjusting the peak i nductor current threshold. power save mode (psm) mode to achieve higher efficiency, the buck regulators i n the ADP5053 smoothly transition to variable frequency psm opera tion when the output load falls below the psm current thresho ld. when the output voltage falls below regulation, the buck regulator enters pwm mode for a few oscillator cycles until t he voltage increases to within regulation. during the idle tim e between bursts, the mosfet turns off, and the output capaci tor supplies all the output current. the psm comparator monitors the internal compensati on node, which represents the peak inductor current informat ion. the average psm current threshold depends on the input voltage (v in ), the output voltage (v out ), the inductor, and the output capacitor. because the output voltage occasionally falls below regulation and then recovers, the output voltage ri pple in psm operation is larger than the ripple in the forced p wm mode of operation under light load conditions. forced pwm and automatic pwm/psm modes the buck regulators can be configured to always ope rate in pwm mode using the sync/mode pin. in forced pwm (fpwm) mode, the regulator continues to operate at a fixed frequency even when the output current is below the pwm/psm t hreshold. in pwm mode, efficiency is lower when compared to p sm mode under light load conditions. the lowside mosfet re mains on when the inductor current falls to less than 0 a, c ausing the ADP5053 to enter continuous conduction mode (ccm). the buck regulators can be configured to operate in automatic pwm/psm mode using the sync/mode pin. in automatic pwm/psm mode, the buck regulators operate in either pwm mode or psm mode, depending on the output current. when the average output current falls below the pwm/psm thre shold, the buck regulator enters psm mode operation; in ps m mode, the regulator operates with a reduced switching fre quency to maintain high efficiency. the lowside mosfet turns off when the output current reaches 0 a, causing the regulat or to operate in discontinuous mode (dcm). when the sync/mode pin is connected to vreg, the pa rt operates in forced pwm (fpwm) mode. when the sync/ mode pin is connected to ground, the part operates in automatic pwm/psm mode. adjustable and fixed output voltages the ADP5053 provides adjustable and fixed output voltage settings via factory fuse. for the adjustable outpu t settings, use an external resistor divider to set the desired out put voltage via the feedback reference voltage (0.8 v for channel 1 to channel 4). for the fixed output settings, the feedback resisto r divider is built into the ADP5053 , and the feedback pin (fbx) must be tied directly to the output. table 8 lists the available fixed output voltage ranges for each buck regulator channel. table 8. fixed output voltage ranges channel fixed output voltage range channel 1 0.85 v to 1.6 v in 25 mv steps channel 2 3.3 v to 5.0 v in 300 mv or 200 mv steps channel 3 1.2 v to 1.8 v in 100 mv steps channel 4 2.5 v to 5.5 v in 100 mv steps the output range can also be programmed by factory fuse. if a different output voltage range is required, contact your local analog devices, inc., sales or distribution represe ntative. internal regulators (vreg and vdd) the internal vreg regulator in the ADP5053 provides a stable 5.1 v power supply for the bias voltage of the mosfe t drivers. the internal vdd regulator in the ADP5053 provides a stable 3.3 v power supply for internal control circuits. c onnect a 1.0 f ceramic capacitor between vreg and ground; connect another 1.0 f ceramic capacitor between vdd and ground. th e internal vreg and vdd regulators are active as long as pvin1 is available. the internal vreg regulator can provide a total loa d of 95 ma including the mosfet driving current, and it can be used as an always alive 5.1 v power supply for a small syste m current
preliminary technical data ADP5053 rev. prb | page 17 of 41 demand. the current limit circuit is included in th e vreg regulator to protect the circuit when the part is h eavily loaded. the vdd regulator is for internal circuit use and i s not recom mended for other purposes. separate supply applications the ADP5053 supports separate input voltages for the four buck regulators. this means that the input voltages for the four buck regulators can be connected to different suppl y voltages. the pvin1 voltage provides the power supply for the internal regulators and the control circuitry. therefore, if the user plans to use separate supply voltages for the buck regula tors, the pvin1 voltage must be above the uvlo threshold before the other channels begin to operate. precision enabling can be used to monitor the pvin1 voltage and to delay the startup of the outputs to ensure t hat pvin1 is high enough to support the outputs in regulation. f or more information, see the precision enabling section. the ADP5053 supports cascading supply operation for the four buck regulators. as shown in figure 32, pvin2, pvin3, and pvin4 are powered from the channel 1 output. in thi s configuration, the channel 1 output voltage must be higher than the uvlo threshold for pvin2, pvin3, and pvin4. pvin1 buck 1 buck 2 v out1 pvin2 to pvin4 v out2 to v out4 v in 11636-037 figure 32. cascading supply application lowside device selection the buck regulators in channel 1 and channel 2 integ rate 4 a highside power mosfets and lowside mosfet drivers . the nchannel mosfets selected for use with the ADP5053 must be able to work with the synchronized buck regulators. in general, a low r dson nchannel mosfet can be used to achieve higher efficiency; dual mosfets in one package (for both c hannel 1 and channel 2) are recommended to save space on the pri nted circuit board (pcb). for more information, see the lowside power device selection section. bootstrap circuitry each buck regulator in the ADP5053 has an integrated bootstrap regulator. the bootstrap regulator requires a 0.1 f ceramic capacitor (x5r or x7r) between the bstx and swx pins to provide the gate drive voltage for the highside mo sfet. active output discharge switch each buck regulator in the ADP5053 integrates a discharge switch from the switching node to ground. this switch is t urned on when its associated regulator is disabled, which he lps to discharge the output capacitor quickly. the typical value of the discharge switch is 250 for channel 1 to channel 4. the disc harge switch function can be enabled or disabled for all four bu ck regulators by factory fuse. precision enabling the ADP5053 has an enable control pin for each regulator. the enable control pin (enx) features a precision enabl e circuit with a 0.8 v reference voltage. when the voltage at the en x pin is greater than 0.8 v, the regulator is enabled. when the volta ge at the enx pin less than 0.725 v, the regulator is disabled. an internal 1 m pulldown resistor prevents errors if the enx pin is left floating. the precision enable threshold voltage allows easy sequencing of channels within the part, as well as sequencing between the ADP5053 and other input/output supplies. the enx pin can a lso be used as a programmable uvlo input using a resist or divider (see figure 33). for more information, see the progr amming the uvlo input section. 0.8v deglitch timer internal enable enx r1 r2 1m input/output voltage ADP5053 11636-038 figure 33. precision enable diagram for one channel oscillator the switching frequency (f sw ) of the ADP5053 can be set to a value from 250 khz to 1.4 mhz by connecting a resistor from the rt pin to ground. the value of the rt resistor can be calculated as follows: r rt (k) = [14,822/ f sw (khz)] 1.081 figure 34 shows the typical relationship between the switching frequency (f sw ) and the rt resistor. the adjustable frequency allows users to make decisions based on the tradeo ff between efficiency and solution size.
ADP5053 preliminary technical data rev. prb | page 18 of 41 1.6m 1.4m 1.2m 1.0m 800k frequenc y (hz) 600k 400k 200k 0 0 20 40 rt resistor (k ) 60 80 11636-039 figure 34. switching frequency vs. rt resistor for channel 1 and channel 3, the frequency can be set to half the master switching frequency set by the rt pin. this setting can be selected by factory fuse. if the master switching f requency is less than 250 khz, this halving of the frequency for chann el 1 or channel 3 is not recommended. phase shift the phase shift between channel 1 and channel 2 and between channel 3 and channel 4 is 180. therefore, channel 3 is in phase with channel 1, and channel 4 is in phase with chann el 2 (see figure 35). this phase shift maximizes the benefits of outofphase operation by reducing the input ripple current and lowering the ground noise. ch2 ch1 (? f sw optional) ch4 sw 180 phase shift 0 reference 0 phase shift 180 phase shift ch3 (? f sw optional) 11636-040 figure 35. phase shift diagram, four buck regulator s synchronization input/output the switching frequency of the ADP5053 can be synchronized to an external clock with a frequency range from 250 khz to 1.4 mhz. the ADP5053 automatically detects the presence of an external clock applied to the sync/mode pin, and the switching frequency transitions smoothly to the fre quency of the external clock. when the external clock signal stops, the device automatically switches back to the internal clock and continues to operate. note that the internal switching frequency set by t he rt pin must be programmed to a value that is close to the exter nal clock value for successful synchronization; the suggested frequ ency difference is less than 15% in typical applications. the sync/mode pin can be configured as a synchroniz ation clock output by factory fuse. a positive clock puls e with a 50% duty cycle is generated at the sync/mode pin with a frequency equal to the internal switching frequency set by th e rt pin. there is a short delay time (approximately 15% of t sw ) from the generated synchronization clock to the channel 1 switching no de. figure 36 shows two ADP5053 devices configured for frequency synchronization mode: one ADP5053 device is configured as the clock output to synchronize another ADP5053 device. it is recommended that a 100 k pullup resistor be used to prevent logic errors when the sync/mode pin is left floatin g. ADP5053 100k vreg sync/mode sync/mode ADP5053 11636-041 figure 36. two ADP5053 devices configured for synchronization mode in the configuration shown in figure 36, the phase shift between channel 1 of the first ADP5053 device and channel 1 of the second ADP5053 device is 0? (see figure 37). ch3 5.00v b w ch1 2.00v b w ch2 5.00v b w m400ns a ch1 560mv 1 2 3 sw1 at first ADP5053 sw1 at second ADP5053 sync-out at first ADP5053 11636-042 figure 37. waveforms of two ADP5053 devices operating in synchronization mode soft start the buck regulators in the ADP5053 include soft start circuitry that ramps the output voltage in a controlled manne r during startup, thereby limiting the inrush current. the s oft start time is typically fixed at 2 ms for each buck regulator when the ss12 and ss34 pins are tied to vreg. to set the soft start time to a value of 2 ms, 4 ms , or 8 ms, connect a resistor divider from the ss12 or ss34 pin to the vr eg pin and ground (see figure 38). this configuration may be r equired to
preliminary technical data ADP5053 rev. prb | page 19 of 41 accommodate a specific startup sequence or an appl ication with a large output capacitor. level detector and decoder vreg top resis tor bottom resis tor ss12 or ss34 ADP5053 11636-043 figure 38. level detector circuit for soft start use the ss12 pin to program the soft start time and parallel operation for channel 1 and channel 2. use the ss34 pi n to program the soft start time for channel 3 and chann el 4. table 9 provides the values of the resistors needed to set the soft start time. table 9. soft start time set by the ss12 and ss34 p ins soft start time r top (k) r bot (k) channel 1 channel 2 channel 3 channel 4 0 n/a 1 2 ms 2 ms 2 ms 2 ms 100 600 2 ms parallel 2 ms 4 ms 200 500 2 ms 8 ms 2 ms 8 ms 300 400 4 ms 2 ms 4 ms 2 ms 400 300 4 ms 4 ms 4 ms 4 ms 500 200 8 ms 2 ms 4 ms 8 ms 600 100 8 ms parallel 8 ms 2 ms n/a 1 0 8 ms 8 ms 8 ms 8 ms 1 n/a = not applicable. parallel operation the ADP5053 supports twophase parallel operation of channel 1 and channel 2 to provide a single output with up to 8 a of current. take the following steps to configure channel 1 and channel 2 as a twophase single output in parallel operation (see figure 39): ? use the ss12 pin to select parallel operation as spe cified in table 9. ? leave the comp2 pin open. ? use the fb1 pin to set the output voltage. ? connect the fb2 pin to ground (fb2 is ignored). ? connect the en2 pin to ground (en2 is ignored). channel 1 buck regulator (4a) channel 2 buck regulator (4a) fb1 pvin1 v out (up to 8a) v in en1 en2 comp1 ss12 sw1 l1 fb2 sw2 l2 pvin2 comp2 vreg 11636-044 figure 39. parallel operation for channel 1 and cha nnel 2 when operating channel 1 and channel 2 in a paralle l configuration, configure the channels as follows: ? set the input voltages and current limit settings f or channel 1 and channel 2 to the same values. ? operate both channels in forced pwm mode. current balance in parallel configuration is well r egulated by the internal control loop. figure 40 shows the typic al current balance matching in the parallel output configurati on. 0 1 2 3 4 5 6 0 2 4 6 8 10 channe l current (a) total output load (a) ch1 ch2 ideal 11636-045 figure 40. current balance in parallel output confi guration, v in = 12 v, v out = 1.2 v, f sw = 600 khz, fpwm mode startup with precharged output the buck regulators in the ADP5053 include a precharged startup feature to protect the lowside mosfets from damage during startup. if the output voltage is precharged before the regulator is turned on, the regulator prevents the reverse in ductor current, which discharges the output capacitor, until the in ternal soft start reference voltage exceeds the precharged voltage on the feedback (fbx) pin.
ADP5053 preliminary technical data rev. prb | page 20 of 41 current limit protection the buck regulators in the ADP5053 include peak current limit protection circuitry to limit the amount of positiv e current flowing through the highside mosfet. the peak current limi t on the power switch limits the amount of current that can flow from the input to the output. the programmable current limit threshold feature allows for the use of small size inductors for low current applications. to configure the current limit threshold for channe l 1, connect a resistor from the dl1 pin to ground. to configure the current limit threshold for channel 2, connect another resis tor from the dl2 pin to ground. table 10 lists the peak current l imit threshold settings for channel 1 and channel 2. table 10. peak current limit threshold settings for channel 1 and channel 2 r ilim1 or r ilim2 typical peak current limit threshold (a) floating 4.4 47 k 2.63 22 k 6.44 the buck regulators in the ADP5053 include negative current limit protection circuitry to limit certain amounts of negative current flowing through the lowside mosfet. frequency foldback the buck regulators in the ADP5053 include frequency foldback to prevent output current runaway when a hard short oc curs on the output. frequency foldback is implemented as follows: ? if the voltage at the fbx pin falls below half the target output voltage, the switching frequency is reduced by half. ? if the voltage at the fbx pin falls again to below onefourth the target output voltage, the switching frequency is reduced to half its current value, that is, to onefourth o f f sw . the reduced switching frequency allows more time fo r the inductor current to decrease but also increases the ripple current during peak current regulation. this results in a r eduction in average current and prevents output current runaway . pulse skip mode under maximum duty cycle under maximum duty cycle conditions, frequency fold back maintains the output in regulation. if the maximum duty cycle is reached, for example, when the input voltage dec reases, the pwm modulator skips every other pwm pulse, resultin g in a switching frequency foldback of onehalf. if the du ty cycle increases further, the pwm modulator skips two of every three pwm pulses, resulting in a switching frequency foldback to one third of the switching frequency. frequency foldback increases t he effective maximum duty cycle, thereby decreasing the dropout voltage between the input and output voltages. hiccup protection the buck regulators in the ADP5053 include a hiccup mode for overcurrent protection (ocp). when the peak inducto r current reaches the current limit threshold, the highside mosfet turns off and the lowside mosfet turns on until the next cycle. when hiccup mode is active, the overcurrent fault c ounter is incremented. if the overcurrent fault counter reach es 15 and overflows (indicating a shortcircuit condition), b oth the high side and lowside mosfets are turned off. the buck regulator remains in hiccup mode for a period equal to seven soft start cycles and then attempts to restart from soft start . if the short circuit fault has cleared, the regulator resumes no rmal operation; otherwise, it reenters hiccup mode after the soft s tart. hiccup protection is masked during the initial soft start cycle to enable startup of the buck regulator under heavy lo ad conditions. note that careful design and proper component selec tion are required to ensure that the buck regulator recovers from hiccup mode under heavy loads. hiccup protection can be en abled or disabled for all four buck regulators by factory fu se. when hiccup protection is disabled, the frequency foldback feat ure is still avail able for overcurrent protection. latchoff protection the buck regulators in the ADP5053 have an optional latchoff mode to protect the device from serious problems su ch as short circuit and overvoltage conditions. latchoff mode can be enabled by factory fuse. short-circuit latch-off mode shortcircuit latchoff mode is enabled by factory fuse (on or off for all four buck regulators). when shortcircuit l atchoff mode is enabled and the protection circuit detects an ov ercurrent status after a soft start, the buck regulator enters hiccu p mode and attempts to restart. if seven continuous restart at tempts are made, and the regulator remains in the fault condition, t he regulator is shut down. this shutdown (latchoff) condition is c leared only by reenabling the channel or by resetting the chann el power supply. note that shortcircuit latchoff mode does not work if hiccup protection is disabled. figure 41 shows the shortcircuit latchoff detectio n function.
preliminary technical data ADP5053 rev. prb | page 21 of 41 output voltage time latch-off latch off this regulator short circuit detected by counter overflow pwrgd 7 t ss scp latch-off function enabled after 7 restart attempts attempt to restart 11636-046 figure 41. short-circuit latch-off detection overvoltage latch-off mode overvoltage latchoff mode is enabled by factory fu se (on or off for all four buck regulators). the overvoltage latc hoff threshold is 124% of the nominal output voltage level. when the output voltage exceeds this threshold, the protection circ uit detects the overvoltage status and the regulator shuts down. th is shutdown (latchoff) condition is cleared only by reenabling the channel or by resetting the channel power supply. figure 42 shows the overvoltage latchoff detection function. output voltage time latch off this regulator latch-off 124% nominal output 100% nominal output chx on 11636-047 figure 42. overvoltage latch-off detection undervoltage lockout (uvlo) undervoltage lockout circuitry monitors the input v oltage level of each buck regulator in the ADP5053 . if any input voltage (pvinx pin) falls below 3.78 v (typical), the corresponding channel is turned off. after the input voltage rises above 4.2 v (typical), the soft start period is initiated, and the correspondi ng channel is enabled when the enx pin is high. note that a uvlo condition on channel 1 (pvin1 pin) has a higher priority than a uvlo condition on other ch annels, which means that the pvin1 supply must be available before other channels can be operated. powergood function the ADP5053 includes an opendrain powergood output (pwrgd pin) that becomes active high when the selec ted buck regulators are operating normally. by default, the pwrgd pin monitors the output voltage on channel 1. other chan nels can be configured to control the pwrgd pin when the ADP5053 is ordered (see table 20). a logic high on the pwrgd pin indicates that the re gulated output voltage of the buck regulator is above 90.5% (typic al) of its nominal output. when the regulated output voltage of the bu ck regulator falls below 87.2% (typical) of its nominal output f or a delay time greater than approximately 50 s, the pwrgd pin goe s low. the output of the pwrgd pin is the logical and of t he internal pwrgx signals. an internal pwrgx signal must be hig h for a validation time of 1 ms before the pwrgd pin goes h igh; if one pwrgx signal fails, the pwrgd pin goes low with no delay. the channels that control the pwrgd pin (channel 1 to ch annel 4) can be specified by factory fuse. the default pwrgd setting is to monitor the output of channel 1. thermal shutdown if the ADP5053 junction temperature exceeds 150 c, the thermal shutdown circuit turns off the ic except for the in ternal linear regulators. extreme junction temperatures can be th e result of high current operation, poor circuit board design, or high ambient temperature. a 15 c hysteresis is included so that the ADP5053 does not return to operation after thermal shutdown until the onchip temperature falls below 135 c. when the part exits thermal shutdown, a soft start is initiated for eac h enabled channel. supervisory the ADP5053 provides microprocessor supply voltage supervision by controlling the reset input of the microprocesso r. code execution errors are avoided during powerup, power down, and brownout conditions by asserting a reset signal whe n the supply voltage is below a preset threshold and by allowing supply voltage stabilization with a fixed timeout reset pulse afte r the supply voltage rises above the threshold. in addition, problems wi th microprocessor code execution can be monitored with a watchdog tim er. be noted the supervisory circuitry is activated only when ei ther enx pin of 4 bucks is high. reset output the ADP5053 has an activelow, opendrain reset output. this output structure requires an external pullup resis tor to connect
ADP5053 preliminary technical data rev. prb | page 22 of 41 the reset output to a voltage rail no higher than 6 v. the resistor must comply with the logic low and logic high volta ge level requirements of the microprocessor while also suppl ying input current and leakage paths on the rsto pin. a 10 k resistor is adequate in most situations. the reset output is asserted when the monitored rai l is below the threshold (v th ), and when wdi is not serviced within the watchdog timeout period (t wd ). reset remains asserted for the duration of the reset active timeout period (t rp ) after v cc rises above the reset threshold or after the watchdog tim er times out. four options can be selected for the reset active t imeout period (t rp ) via factory fuse: 1.4 ms, 28 ms, 200 ms (default) , and 1600 ms. figure 43 illustrates the behavior of the reset outp uts, assuming that v out2 is selected as the rail to be monitored and suppli es the external pullup connected to the rsto output. t rp t rd v out2 v th v th v out2 1v 0v 0v v out2 11636-048 rsto figure 43. reset timing diagram the ADP5053 has a dedicated sensing input pin (vth) that monitors the supply rail. the reset threshold at th e vth input is typically 0.5 v. to monitor a voltage greater th an 0.5 v, connect a resistor divider network to the device. do not allow the vth input to float or be grounded. instead, connect it to a supply voltage greater than its spe cified threshold voltage. a small capacitor can be added on the vth pin to improve noise rejection and false reset generation. when monitoring the input voltage, if the selected reset threshold falls below the internal vdd regulator uvlo level, the reset output ( rsto ) asserts low as soon as the internal vdd regulator falls below the uvlo threshold. the reset output is then kept low down to ~1 v vdd to ensure that the reset output is not released when there is insufficient voltage on the rail, whi ch then supplies a processor to restart the processor opera tions. watchdog input the ADP5053 features a watchdog timer that monitors microprocessor activity. a timer circuit is cleared with every lowtohigh or hightolow logic transition on the watchdog input pin (wdi), which detects pulses as short as 80 ns. if the timer counts through the preset watchdog timeout pe riod (t wd ), reset is asserted. the microprocessor is required t o toggle the wdi pin to avoid being reset. therefore, failure of the microprocessor to toggle the wdi within the timeout period indicat es a code execution error, and the reset pulse generated rest arts the micro processor in a known state. four options can be sel ected for the watchdog timeout period (t wd via factory fuse: 6.3 ms, 102 ms, 1600 ms (default), and 25.6 sec. in addition to the logic transition on the wdi, the watchdog timer is also cleared by a reset assertion due to a n undervoltage condition on v out2 . when a reset is asserted, the watchdog timer is cleared, and it does not begin counting again un til the reset deasserts. the watchdog timer can be disabled by le aving wdi floating or by threestating the wdi driver (see fi gure 44). v th v out2 v out2 wdi 1v 0v 0v 0v v out2 v out2 t rp t rp t wd 11636-049 rsto figure 44. watchdog timing diagram manual reset input the ADP5053 features a manual reset input ( mr pin, active low) with two operation modes available: processor manua l reset mode, or power on/off switch mode. the mr operation mode selection can be configured by factory fuse, and th e default setting is the processor manual reset mode. the mr input has a 55 k, internal pullup resistor so tha t the input remains high when unconnected. to generate a reset, an external pushbutton switch can be connected between mr and ground. noise immunity is provided on the mr input, and fast, negativegoing transients of up to 100 ns (typical) a re ignored. a 0.1 f capacitor between mr and ground provides additional noise immunity. processor manual reset mode in processor manual reset mode, when mr is driven low, the reset output is asserted. when mr transitions from low to high, the reset remains asserted for the duration of the reset active timeout period (t rp ) before deasserting. figure 45 shows the mr behavior of the processor manual reset mode. mr mr externally driven low rsto v cc t rp t rp v rt v rt 11636-050 figure 45. mr timing diagram in processor reset mode power on/off switch mode in power on/off switch mode, when mr is driven low for more than 4 sec, all channels (when enabled) in the ADP5053 shut down, and internal control registers are reset. in shutdown standby condition, if mr is driven low for 500 ms again, all channels (when enabled) in the ADP5053 start up again according to the individual en pin status for a proper startup seque nce on all channels.
preliminary technical data ADP5053 rev. prb | page 23 of 41 the mr timing diagram in power on/off switch mode is show n in figure 46. to prepare for an automatic startup next time, the mr shutdown condition can be cleared by either of the following conditions: a power reset condition, where all external enx pins are pulled down, and pull up. 11636-051 500ms 4s 1s blanking t rp t rp sequence start up sequence start up mr shutdown by 4s mr timer mr shutdown status force rsto low in shutdown status restart up all powers by 500ms mr timer mr (used as on/off switch) vout1 to vout4 vinx/enx rsto figure 46. mr timing diagram in power on/off switch mode
ADP5053 preliminary technical data rev. prb | page 24 of 41 applications information adisimpower design tool the ADP5053 is supported by the adisimpower ? design tool set. adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal. the tools enable the user to generate a full schematic and bi ll of materials and to calculate performance in minutes. adisimpower can optimize designs for cost, area, efficiency, and pa rt count while taking into consideration the operating conditions and limitations of the ic and all real external components. the adisimpower tool can be found at www.analog.com/adisimpower , and the user can request an unpopulated board through the t ool. programming the adjustable output voltage the output voltage of the ADP5053 is externally set by a resistive voltage divider from the output voltage to the fbx pin. to limit the degradation of the output voltage accuracy due to feedback bias current, ensure that the bottom resistor in th e divider is not too large; a value of less than 50 k is recommended . the equation for the output voltage setting is v out = v ref (1 + ( r top / r bot )) where: v out is the output voltage. v ref is the feedback reference voltage (0.8 v for channel 1 to channel 4). r top is the feedback resistor from v out to fbx. r bot is the feedback resistor from fbx to ground. no resistor divider is required in the fixed output options. if a different fixed output voltage is required, conta ct your local analog devices sales or distribution representative . voltage conversion limitations for a given input voltage, upper and lower limitati ons on the output voltage exist due to the minimum on time and the minimum off time. the minimum output voltage for a given input voltag e and switching frequency is limited by the minimum on ti me. the minimum on time for channel 1 and channel 2 is 117 ns (typical), and the minimum on time for channel 3 an d channel 4 is 90 ns (typical). the minimum on time increases at higher junction temperatures. note that in forced pwm mode, channel 1 and channel 2 can potentially exceed the nominal output voltage when the minimum on time limit is exceeded. careful switching freque ncy selection is required to avoid this problem. the minimum output voltage in continuous conduction mode (ccm) for a given input voltage and switching frequ ency can be calculated using the following equation: v out_min = v in t min_on f sw ? ( r dson1 ? r dson2 ) i out_min t min_on f sw ? ( r dson2 + r l ) i out_min (1) where: v out_min is the minimum output voltage. t min_on is the minimum on time. f sw is the switching frequency. r dson1 is the on resistance of the highside mosfet. r dson2 is the on resistance of the lowside mosfet. i out_min is the minimum output current. r l is the resistance of the output inductor. the maximum output voltage for a given input voltag e and switching frequency is limited by the minimum off t ime and the maximum duty cycle. note that the frequency foldbac k feature helps to increase the effective maximum duty cycle by lowering the switching frequency, thereby decreasing the dro pout voltage between the input and output voltages (see the freq uency foldback section). the maximum output voltage for a given input voltag e and switching frequency can be calculated using the fol lowing equation: v out_max = v in (1 ? t min_off f sw ) ? ( r dson1 ? r dson2 ) i out_max (1 ? t min_off f sw ) ? ( r dson2 + r l ) i out_max (2) where: v out_max is the maximum output voltage. t min_off is the minimum off time. f sw is the switching frequency. r dson1 is the on resistance of the highside mosfet. r dson2 is the on resistance of the lowside mosfet. i out_max is the maximum output current. r l is the resistance of the output inductor. as shown in equation 1 and equation 2, reducing the switching frequency eases the minimum on time and off time li mitations. current limit setting the ADP5053 has three selectable current limit thresholds for channel 1 and channel 2. make sure that the selected current limit value is larger than the peak current of the inductor, i peak . see table 10 for the current limit configuration for channel 1 and channel 2.
preliminary technical data ADP5053 rev. prb | page 25 of 41 soft start setting the buck regulators in the ADP5053 include soft start circuitry that ramps the output voltage in a controlled manne r during startup, thereby limiting the inrush current. to se t the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect a r esistor divider from the ss12 or ss34 pin to the vreg pin and ground (see the soft start section). inductor selection the inductor value is determined by the switching f requency, input voltage, output voltage, and inductor ripple current. using a small inductor value yields faster transient resp onse but degrades efficiency due to the larger inductor ripple curren t. using a large inductor value yields a smaller ripple current and better efficiency but results in slower transient response. thus, a t radeoff must be made between transient response and efficiency. as a guideline, the inductor ripple current, i l , is typically set to a value from 30% to 40% of the maximum load current. the inductor va lue can be calculated using the following equation: l = [( v in ? v out ) d ]/( i l f sw ) where: v in is the input voltage. v out is the output voltage. d is the duty cycle ( d = v out / v in ). i l is the inductor ripple current. f sw is the switching frequency. the ADP5053 has internal slope compensation in the current loop to prevent subharmonic oscillations when the d uty cycle is greater than 50%. because the internal current sen se signal is required, the inductor value recommended must not b e larger than 10 h for ch1 and ch2 or 22 h for ch3 and ch4. the peak inductor current is calculated using the f ollowing equation: i peak = i out + ( i l /2) the saturation current of the inductor must be larg er than the peak inductor current. for ferrite core inductors w ith a fast saturation characteristic, make sure that the satur ation current rating of the inductor is higher than the current l imit threshold of the buck regulator to prevent the inductor from becoming saturated. the rms current of the inductor can be calculated u sing the following equation: 12 2 2 l out rms i i i ? + = shielded ferrite core materials are recommended for low core loss and low emi. table 11 lists recommended induct ors. table 11. recommended inductors vendor part no. value (h) i sat (a) i rms (a) dcr (m) size (mm) coilcraft xfl4020102 1.0 5.4 11 10.8 4 4 xfl4020222 2.2 3.7 8.0 21.35 4 4 xfl4020332 3.3 2.9 5.2 34.8 4 4 xfl4020472 4.7 2.7 5.0 52.2 4 4 xal4030682 6.8 3.6 3.9 67.4 4 4 xal4040103 10 3.0 3.1 84 4 4 xal6030102 1.0 23 18 5.62 6 6 xal6030222 2.2 15.9 10 12.7 6 6 xal6030332 3.3 12.2 8.0 19.92 6 6 xal6060472 4.7 10.5 11 14.4 6 6 xal6060682 6.8 9.2 9.0 18.9 6 6 toko fdv05301r0 1.0 11.2 9.1 9.4 6.2 5.8 fdv05302r2 2.2 7.1 7.0 17.3 6.2 5.8 fdv05303r3 3.3 5.5 5.3 29.6 6.2 5.8 fdv05304r7 4.7 4.6 4.2 46.6 6.2 5.8 output capacitor selection the selected output capacitor affects both the outp ut voltage ripple and the loop dynamics of the regulator. for example, during load step transients on the output, when the load is suddenly increased, the output capacitor supplies t he load until the control loop can ramp up the inductor current, causing an undershoot of the output voltage. the output capacitance required to meet the undersh oot (voltage droop) requirement can be calculated using the following equation: ( ) uv out out in step uv uv out v v v l i k c _ 2 _ 2 ? ? ? = where: k uv is a factor (typically set to 2). i step is the load step. v out_uv is the allowable undershoot on the output voltage. another example of the effect of the output capacit or on the loop dynamics of the regulator is when the load is sudde nly removed from the output and the energy stored in the induct or rushes into the output capacitor, causing an overshoot of the o utput voltage.
ADP5053 preliminary technical data rev. prb | page 26 of 41 the output capacitance required to meet the oversho ot requirement can be calculated using the following e quation: ( ) 2 2 2 _ out out_ov out step ov ov out v v v l i k c ? ? + ? = where: k ov is a factor (typically set to 2). i step is the load step. v out_ov is the allowable overshoot on the output voltage. the equivalent series resistance (esr) of the outpu t capacitor and its capacitance value determine the output volt age ripple. use the following equations to select a capacitor t hat can meet the output ripple requirements: ripple out sw l ripple out v f i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _ where: i l is the inductor ripple current. f sw is the switching frequency. v out_ripple is the allowable output voltage ripple. r esr is the equivalent series resistance of the output capacitor. select the largest output capacitance given by c out_uv , c out_ov , and c out_ripple to meet both load transient and output ripple requirements. the voltage rating of the selected output capacitor must be greater than the output voltage. the minimum rms cu rrent rating of the output capacitor is determined by the following equation: 12 _ l rms c i i out ? = input capacitor selection the input decoupling capacitor attenuates high freq uency noise on the input and acts as an energy reservoir. use a ce ramic capacitor and place it close to the pvinx pin. keep the loop composed of the input capacitor, the highside nfet, and the lo wside nfet as small as possible. the voltage rating of the inp ut capacitor must be greater than the maximum input voltage. mak e sure that the rms current rating of the input capacitor is la rger than the following equation: ( ) d d i i out rms c in ? = 1 _ where d is the duty cycle ( d = v out / v in ). lowside power device selection channel 1 and channel 2 include integrated lowside mosfet drivers that can drive lowside nchannel mosfets ( nfets). the selection of the lowside nchannel mosfet affe cts the performance of the buck regulator. the selected mosfet must meet the following require ments: ? draintosource voltage (v ds ) must be higher than 1.2 v in . ? drain current (i d ) must be greater than 1.2 i limit_max , where i limit_max is the selected maximum current limit threshold. ? the selected mosfet can be fully turned on at v gs = 4.5 v. ? total gate charge (qg at v gs = 4.5 v) must be less than 20 nc. lower qg characteristics provide higher efficiency. when the highside mosfet is turned off, the lowsi de mosfet supplies the inductor current. for low duty cycle a pplications, the lowside mosfet supplies the current for most of th e period. to achieve higher efficiency, it is important to se lect a mosfet with low on resistance. the power conduction loss f or the low side mosfet can be calculated using the following e quation: p fet_low = i out 2 r dson (1 ? d ) where: r dson is the on resistance of the lowside mosfet. d is the duty cycle ( d = v out / v in ). table 12 lists recommended dual mosfets for various current limit settings. ensure that the mosfet can handle t hermal dissipation due to power loss. table 12. recommended dual mosfets vendor part no. v ds (v) i d (a) r dson (m) qg (nc) size (mm) ir irfhm8363 30 10 20.4 6.7 3 3 irlhs6276 20 3.4 45 3.1 2 2 fairchild fdma1024 20 5.0 54 5.2 2 2 fdmb3900 25 7.0 33 11 3 2 fdmb3800 30 4.8 51 4 3 2 fdc6401 20 3.0 70 3.3 3 3 vishay si7228dn 30 23 25 4.1 3 3 si7232dn 20 25 16.4 12 3 3 si7904bdn 20 6 30 9 3 3 si5906du 30 6 40 8 3 2 si5908dc 20 5.9 40 5 3 2 sia906edj 20 4.5 46 3.5 2 2 aos aon7804 30 22 26 7.5 3 3 aon7826 20 22 26 6 3 3 ao6800 30 3.4 70 4.7 3 3 aon2800 20 4.5 47 4.1 2 2 programming the uvlo input the precision enable input can be used to program t he uvlo threshold of the input voltage, as shown in figure 33. to limit
preliminary technical data ADP5053 rev. prb | page 27 of 41 the degradation of the input voltage accuracy due t o the internal 1 m pulldown resistor tolerance, ensure that the bottom resistor in the divider is not too large; a value o f less than 50 k is recommended. the precision turnon threshold is 0.8 v. the resis tive voltage divider for the programmable v in startup voltage is calculated as follows: ) m 1 + m 1 + ( )) v/ (0.8 + na (0.8 = bot_en bot_en top_en bot_en in_startup r r r r v where: r top_en is the resistor from v in to en. r bot_en is the resistor from en to ground. compensation components design for the peak current mode control architecture, the power stage can be simplified as a voltage controlled current s ource that supplies current to the output capacitor and load r esistor. the simplified loop is composed of one domain pole and a zero contributed by the output capacitor esr. the contro ltooutput transfer function is shown in the following equatio ns: ? ?? ? ? ?? ? + ? ?? ? ? ?? ? + = = p z vi comp out vd f s f s r a s v s v s g 2 1 2 1 ) ( ) ( ) ( out esr z c r f = 2 1 ( ) out esr p c r r f + = 2 1 where: a vi = 10 a/v for channel 1 or channel 2, and 3.33 a/v for channel 3 or channel 4. r is the load resistance. r esr is the equivalent series resistance of the output capacitor. c out is the output capacitance. the ADP5053 uses a transconductance amplifier as the error amplifier to compensate the system. figure 47 shows the simplified peak current mode control small signal c ircuit. r esr r + ? g m r c c cp c out c c r top r bot ? + a vi v out v comp v out 11636-052 figure 47. simplified peak current mode control sma ll signal circuit the compensation components, r c and c c , contribute a zero; r c and the optional c cp contribute an optional pole. the closedloop transfer equation is as follows: ) ( 1 1 ) ( s g s c c c c r s s c r c c g r r r s t vd cp c cp c c c c cp c m top bot bot v ? ?? ? ? ?? ? + + + + ? + = the following guidelines show how to select the com pensation components (r c , c c , and c cp ) for ceramic output capacitor applications. 1. determine the cross frequency (f c ). generally, f c is between f sw /12 and f sw /6. 2. calculate r c using the following equation: vi m c out out c a g f c v r = v 8.0 2 3. place the compensation zero at the domain pole (f p ). calculate c c using the following equation: ( ) c out esr c r c r r c + = 4. c cp is optional. it can be used to cancel the zero cau sed by the esr of the output capacitor. calculate c cp using the following equation: c out esr cp r c r c = power dissipation the total power dissipation in the ADP5053 simplifies to p d = p buck1 + p buck2 + p buck3 + p buck4
ADP5053 preliminary technical data rev. prb | page 28 of 41 buck regulator power dissipation the power dissipation (p loss ) for each buck regulator includes power switch conduction losses (p cond ), switching losses (p sw ), and transition losses (p tran ). other sources of power dissipation exist, but these sources are generally less signifi cant at the high output currents of the application thermal limit. use the following equation to estimate the power di ssipation of the buck regulator: p loss = p cond + p sw + p tran power switch conduction loss (p cond ) power switch conduction losses are caused by the fl ow of output current through both the highside and lowside pow er switches, each of which has its own internal on resistance (r dson ). use the following equation to estimate the power sw itch conduction loss: p cond = ( r dson_hs d + r dson_ls (1 ? d )) i out 2 where: r dson_hs is the on resistance of the highside mosfet. r dson_ls is the on resistance of the lowside mosfet. d is the duty cycle ( d = v out / v in ). switching loss (p sw ) switching losses are associated with the current dr awn by the driver to turn the power devices on and off at the switching frequency. each time a power device gate is turned on or off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. use the following equation to estimate the switching loss: p sw = ( c gate_hs + c gate_ls ) v in 2 f sw where: c gate_hs is the gate capacitance of the highside mosfet. c gate_ls is the gate capacitance of the lowside mosfet. f sw is the switching frequency. transition loss (p tran ) transition losses occur because the highside mosfe t cannot turn on or off instantaneously. during a switch nod e transition, the mosfet provides all the inductor current. the s ourceto drain voltage of the mosfet is half the input volta ge, resulting in power loss. transition losses increase with both load and input voltage and occur twice for each switching cycle. u se the following equation to estimate the transition loss: p tran = 0.5 v in i out ( t r + t f ) f sw where: t r is the rise time of the switch node. t f is the fall time of the switch node. thermal shutdown channel 1 and channel 2 store the value of the indu ctor current only during the on time of the internal highside m osfet. therefore, a small amount of power (as well as a sm all amount of input rms current) is dissipated inside the ADP5053 , which reduces thermal constraints. however, when channel 1 and channel 2 are operating under maximum load with high ambient temperature and high duty cycle, the input rms current can become very large and cause the junction temperature to exceed the maximum junc tion temperature of 125c. if the junction temperature e xceeds 150c, the regulator enters thermal shutdown and re covers when the junction temperature falls below 135c. junction temperature the junction temperature of the die is the sum of t he ambient temperature of the environment and the temperature rise of the package due to power dissipation, as shown in the f ollowing equation: t j = t a + t r where: t j is the junction temperature. t a is the ambient temperature. t r is the rise in temperature of the package due to p ower dissipation. the rise in temperature of the package is directly proportional to the power dissipation in the package. the propor tionality constant for this relationship is the thermal resis tance from the junction of the die to the ambient temperature, as shown in the following equation: t r = ja p d where: t r is the rise in temperature of the package. ja is the thermal resistance from the junction of the die to the ambient temperature of the package (see table 6). p d is the power dissipation in the package. an important factor to consider is that the thermal resistance value is based on a 4layer, 4 inch 3 inch pcb wi th 2.5 oz. of copper, as specified in the jedec standard, whereas realworld applications may use pcbs with different dimensions and a different number of layers. it is important to maximize the amount of copper us ed to remove heat from the device. copper exposed to air dissipa tes heat better
preliminary technical data ADP5053 rev. prb | page 29 of 41 than copper used in the inner layers. connect the e xposed pad to the ground plane with several vias.
ADP5053 preliminary technical data rev. prb | page 30 of 41 design example this section provides an example of the stepbyste p design procedures and the external components required for channel 1. table 13 lists the design requirements for this exa mple. table 13. example design requirements for channel 1 parameter specification input voltage v pvin1 = 12 v 5% output voltage v out1 = 1.2 v output current i out1 = 4 a output ripple v out1_ripple = 12 mv in ccm mode load transient 5% at 20% to 80% load transient, 1 a/s although this example shows stepbystep design pro cedures for channel 1, the procedures apply to all other bu ck regulator channels (channel 2 to channel 4). setting the switching frequency the first step is to determine the switching freque ncy for the ADP5053 design. in general, higher switching frequencies produce a smaller solution size due to the lower co mponent values required, whereas lower switching frequencie s result in higher conversion efficiency due to lower switching losses. the switching frequency of the ADP5053 can be set to a value from 250 khz to 1.4 mhz by connecting a resistor fr om the rt pin to ground. the selected resistor allows the use r to make decisions based on the tradeoff between efficiency and solution size. (for more information, see the oscil lator section.) however, the highest supported switching frequency must be assessed by checking the voltage conversion limitat ions enforced by the minimum on time and the minimum off time (see the voltage conversion limitations section). in this design example, a switching frequency of 60 0 khz is used to achieve a good combination of small solutio n size and high conversion efficiency. to set the switching fr equency to 600 khz, use the following equation to calculate th e resistor value, r rt : r rt (k) = [14,822/ f sw (khz)] 1.081 therefore, select standard resistor r rt = 31.6 k. setting the output voltage select a 10 k bottom resistor (r bot ) and then calculate the top feedback resistor using the following equation: r bot = r top ( v ref /( v out ? v ref )) where: v ref is 0.8 v for channel 1. v out is the output voltage. to set the output voltage to 1.2 v, choose the foll owing resistor values: r top = 4.99 k, and r bot = 10 k. setting the current limit for 4 a output current operation, the typical peak current limit is 6.44 a. for this example, choose r ilim1 = 22 k (see table 10). for more information, see the current limit protect ion section. selecting the inductor the peaktopeak inductor ripple current, i l , is set to 35% of the maximum output current. use the following equat ion to estimate the value of the inductor: l = [( v in ? v out ) d ]/( i l f sw ) where: v in = 12 v. v out = 1.2 v. d is the duty cycle ( d = v out / v in = 0.1). i l = 35% 4 a = 1.4 a. f sw = 600 khz. the resulting value for l is 1.28 h. the closest s tandard inductor value is 1.5 h; therefore, the inductor r ipple current, i l , is 1.2 a. the peak inductor current is calculated using the f ollowing equation: i peak = i out + ( i l /2) the calculated peak current for the inductor is 4.6 a. the rms current of the inductor can be calculated u sing the following equation: 12 2 2 l out rms i i i ? + = the rms current of the inductor is approximately 4. 02 a. therefore, an inductor with a minimum rms current r ating of 4.02 a and a minimum saturation current rating of 4 .6 a is required. however, to prevent the inductor from rea ching its saturation point in current limit conditions, it is recommended that the inductor saturation current be higher than the maximum peak current limit, typically 7.48 a, for reliable operation. based on these requirements and recommendations, th e toko fdv05301r5, with a dcr of 13.5 m, is selected for this design.
preliminary technical data ADP5053 rev. prb | page 31 of 41 selecting the output capacitor the output capacitor must meet the output voltage r ipple and load transient requirements. to meet the output vol tage ripple requirement, use the following equations to calcula te the esr and capacitance: ripple out sw l ripple out v f i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _ the calculated capacitance, c out_ripple , is 20.8 f, and the calculated r esr is 10 m. to meet the 5% overshoot and undershoot requiremen ts, use the following equations to calculate the capacitanc e: ( ) uv out out in step uv uv out v v v l i k c _ 2 _ 2 ? ? ? = ( ) 2 2 2 _ out out_ov out step ov ov out v v v l i k c ? ? + ? = for estimation purposes, use k ov = k uv = 2; therefore, c out_ov = 117 f and c out_uv = 13.3 f. the esr of the output capacitor must be less than 1 3.3 m, and the output capacitance must be greater than 117 f. it is recommended that three ceramic capacitors be used (47 f, x5r, 6.3 v), such as the grm21br60j476me15 from murata with an esr of 2 m. selecting the lowside mosfet a low r dson nchannel mosfet must be selected for high efficiency solutions. the mosfet breakdown voltage (v ds ) must be greater than 1.2 v in , and the drain current must be greater than 1.2 i limit_max . it is recommended that a 20 v, dual nchannel mosfe t, such as the si7232dn from vishay, be used for both chann el 1 and channel 2. the r dson of the si7232dn at 4.5 v driver voltage is 16.4 m, and the total gate charge is 12 nc. designing the compensation network for better load transient and stability performance , set the cross frequency, f c , to f sw /10. in this example, f sw is set to 600 khz; therefore, f c is set to 60 khz. for the 1.2 v output rail, the 47 f ceramic output capacitor has a derated value of 40 f. k 14.4 a/v 10 s 470 v 0.8 khz 60 f 40 3 v 1.2 2 = = c r ( ) nf 2.51 k 14.4 f 40 3 0.001 0.3 = + = c c pf 8.3 k 14.4 f 40 3 0.001 = = cp c choose standard components: r c = 15 k and c c = 2.7 nf. c cp is optional. figure 48 shows the bode plot for the 1.2 v output rail. the cross frequency is 62 khz, and the phase margin is 58. figure 49 shows the load transient waveform. 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 120 ?180 ?150 ?120 ?90 ?60 ?30 0 30 60 90 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 62khz phase margin: 58 11636-053 figure 48. bode plot for 1.2 v output ch1 50.0mv b w ch4 2.00a b w m200s a ch4 2.32a 1 4 v out i out 11636-054 figure 49. 0.8 a to 3.2 a load transient for 1.2 v output selecting the soft start time the soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overs hoot during soft start and limiting the inrush current. the ss12 pin can be used to program a soft start ti me of 2 ms, 4 ms, or 8 ms and can also be used to configure par allel operation of channel 1 and channel 2. for more information, s ee the soft start section and table 9. selecting the input capacitor for the input capacitor, select a ceramic capacitor with a minimum value of 10 f; place the input capacitor close to the pvin1 pin. in this example, one 10 f, x5r, 25 v ceramic capac itor is recommended.
ADP5053 preliminary technical data rev. prb | page 32 of 41 recommended external components table 14 lists the recommended external components for 4 a applications used with channel 1 and channe l 2 of the ADP5053 . table 15 lists the recommended external components for 1.2 a applications used with channel 3 and channel 4. table 14. recommended external components for typic al 4 a applications, channel 1 and channel 2 (1% o utput ripple, 7.5% tolerance at ~60% step transient) f sw (khz) i out (a) v in (v) v out (v) l (h) c out (f) r top (k) r bot (k) r c (k) c c (pf) dual fet 300 4 12 (or 5) 1.2 3.3 2 100 1 4.99 10 10 4700 si7232dn 12 (or 5) 1.5 3.3 2 100 1 8.87 10.2 10 4700 si7232dn 12 (or 5) 1.8 3.3 3 47 2 12.7 10.2 6.81 4700 si7232dn 12 (or 5) 2.5 4.7 3 47 2 21.5 10.2 10 4700 si7232dn 12 (or 5) 3.3 6.8 3 47 2 31.6 10.2 10 4700 si7232dn 12 5.0 6.8 47 3 52.3 10 4.7 4700 si7232dn 600 4 12 (or 5) 1.2 1.5 2 47 2 4.99 10 10 2700 si7232dn 12 (or 5) 1.5 1.5 2 47 2 8.87 10.2 10 2700 si7232dn 12 (or 5) 1.8 2.2 2 47 2 12.7 10.2 10 2700 si7232dn 12 (or 5) 2.5 2.2 2 47 2 21.5 10.2 10 2700 si7232dn 12 (or 5) 3.3 3.3 2 47 2 31.6 10.2 15 2700 si7232dn 12 5.0 3.3 47 3 52.3 10 10 2700 si7232dn 1000 4 5 1.2 1.0 2 47 2 4.99 10 15 1500 si7232dn 5 1.5 1.0 2 47 2 8.87 10.2 15 1500 si7232dn 12 (or 5) 1.8 1.0 47 2 12.7 10.2 10 1500 si7232dn 12 (or 5) 2.5 1.5 47 2 21.5 10.2 10 1500 si7232dn 12 (or 5) 3.3 1.5 47 2 31.6 10.2 10 1500 si7232dn 12 5.0 2.2 47 3 52.3 10 15 1500 si7232dn 1 100 f capacitor: murata grm31cr60j107me39 (6.3 v, x5r, 1206). 2 47 f capacitor: murata grm21br60j476me15 (6.3 v, x 5r, 0805). 3 47 f capacitor: murata grm31cr61a476me15 (10 v, x5 r, 1206). table 15. recommended external components for typic al 1.2 a applications, channel 3 and channel 4 (1% output ripple, 7.5% tolerance at ~60% step transient) f sw (khz) i out (a) v in (v) v out (v) l (h) c out (f) r top (k) r bot (k) r c (k) c c (pf) 300 1.2 12 (or 5) 1.2 10 2 22 1 4.99 10 6.81 4700 12 (or 5) 1.5 10 2 22 1 8.87 10.2 6.81 4700 12 (or 5) 1.8 15 2 22 1 12.7 10.2 6.81 4700 12 (or 5) 2.5 15 2 22 1 21.5 10.2 6.81 4700 12 (or 5) 3.3 22 2 22 1 31.6 10.2 6.81 4700 12 5.0 22 22 2 52.3 10 6.81 4700 600 1.2 12 (or 5) 1.2 4.7 22 1 4.99 10 6.81 2700 12 (or 5) 1.5 6.8 22 1 8.87 10.2 6.81 2700 12 (or 5) 1.8 6.8 22 1 12.7 10.2 6.81 2700 12 (or 5) 2.5 10 22 1 21.5 10.2 6.81 2700 12 (or 5) 3.3 10 22 1 31.6 10.2 6.81 2700 12 5.0 10 22 2 52.3 10 6.81 2700 1000 1.2 5 1.2 2.2 22 1 4.99 10 10 1800 12 (or 5) 1.5 3.3 22 1 8.87 10.2 10 1800 12 (or 5) 1.8 4.7 22 1 12.7 10.2 10 1800 12 (or 5) 2.5 4.7 22 1 21.5 10.2 10 1800 12 (or 5) 3.3 6.8 22 1 31.6 10.2 10 1800 12 5.0 6.8 22 2 52.3 10 15 1800 1 22 f capacitor: murata grm188r60j226mea0 (6.3 v, x 5r, 0603).
preliminary technical data ADP5053 rev. prb | page 33 of 41 2 22 f capacitor: murata grm219r61a226mea0 (10 v, x5 r, 0805).
ADP5053 preliminary technical data rev. prb | page 34 of 41 circuit board layout recommendations good circuit board layout is essential to obtain th e best perfor mance from the ADP5053 (see figure 51). poor layout can affect the regulation and stability of the part, as well a s the electro magnetic interference (emi) and electromagnetic com patibility (emc) performance. refer to the following guideline s for a good pcb layout. ? place the input capacitor, inductor, mosfet, output capacitor, and bootstrap capacitor close to the ic. ? use short, thick traces to connect the input capaci tors to the pvinx pins, and use dedicated power ground to c onnect the input and output capacitor grounds to minimize the connection length. ? use several high current vias, if required, to conn ect pvinx, pgndx, and swx to other power planes. ? use short, thick traces to connect the inductors to the swx pins and the output capacitors. ? ensure that the high current loop traces are as sho rt and wide as possible. figure 50 shows the high current path. ? maximize the amount of ground metal for the exposed pad, and use as many vias as possible on the component s ide to improve thermal dissipation. ? use a ground plane with several vias connecting to the com ponent side ground to further reduce noise interfer ence on sensitive circuit nodes. ? place the decoupling capacitors close to the vreg a nd vdd pins. ? place the frequency setting resistor close to the r t pin. ? place the feedback resistor divider close to the fb x pin. in addition, keep the fbx traces away from the high cu rrent traces and the switch node to avoid noise pickup. ? use 0402 or 0603 size resistors and capacitors to a chieve the smallest possible footprint solution on boards where space is limited. v in v out pvinx enx pgnd bstx swx ADP5053 dlx fbx 11636-055 figure 50. typical circuit with high current traces shown in blue ADP5053 a d p 5 0 5 3 l1 l3 l4 dual mosfet l2 l 1 l 2 vout4 vout3 vout2 vout1 11636-056 figure 51. typical pcb layout for the ADP5053
preliminary technical data ADP5053 rev. prb | page 35 of 41 typical application circuits vreg channel 2 buck regulator (1.2a/2.5a/4a) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 2.2h 4.7h 6.8h 10h l2 5v reg sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 vreg l3 bst3 sw3 fb3 pgnd3 l4 bst4 sw4 fb4 pgnd4 vreg vreg pvin1 comp1 en1 pvin2 en2 pvin3 ss34 comp3 en3 pvin4 comp4 en4 c2 10f 4.7nf 4.7k 31.6k 2.7nf 6.81k 2.7nf 6.81k c1 1.0f c4 47f c3 0.1f c5 10f c6 0.1f c8 10f c9 0.1f c10 22f c11 10f c12 0.1f c13 22f 12v vout1 vout2 vout3 1.2v/2.5a vcore i/o int scl sda 1.5v/1.2a 4.0v ~ 4.5v/1.2a (dvs) vout4 5v reg exposed pad ss12 c0 1.0f vdd watchdog and reset wdi vth ADP5053 channel 1 buck regulator (1.2a/2.5a/4a) channel 4 buck regulator (1.2a) c7 47f comp2 4.7nf 4.7k vreg 3.3v/2.5a vout1 10k 10k 10k sia906edj (46m ) 11636-058 ddr termination ldo ddr memory processor rfpa rf transceiver rsto mr figure 52. typical femtocell application, 600 khz s witching frequency, fixed output model
ADP5053 preliminary technical data rev. prb | page 36 of 41 vreg channel 2 buck regulator (1.2a/2.5a/4a) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 1.5h 2.2h 6.8h 10h l2 5v reg sync/mode fb1 r t bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 vreg l3 bst3 sw3 fb3 pgnd3 l4 bst4 sw4 fb4 pgnd4 vreg vreg pvin1 comp1 en1 pvin2 en2 pvin3 ss34 comp3 en3 pvin4 comp4 en4 c2 10f 4.7nf 10k 31.6k 2.7nf 6.81k 2.7nf 6.81k c1 1.0f c4 47f c3 0.1f c5 10f c6 0.1f c8 10f c9 0.1f c10 22f c11 10f c12 0.1f c13 22f 12v vout1 vout2 vout3 1.2v/4a vcore 1.5v/1.2a 3.3v/1.2a vout4 5v reg exposed pad ss12 c0 1.0f vdd watchdog and reset wdi vth ADP5053 channel 1 buck regulator (1.2a/2.5a/4a) channel 4 buck regulator (1.2a) c18 47f c7 47f c19 47f comp2 4.7nf 10k vreg nreset gpio rsto wdi 2.5v/4a vout1 rsto 10k 11k 10k 10.2k 10.2k 31.6k 8.87k 4.99k 10k si7232dn (16.4m ) ddr3 memory i/os bank 3 flash memory processor bank 2 i/os auxiliary voltage fpga bank 1 bank 0 11636-059 ddr termination ldo 22k 22k mr figure 53. typical fpga application, 600 khz switch ing frequency, adjustable output model
preliminary technical data ADP5053 rev. prb | page 37 of 41 vreg vreg channel 2 buck regulator (1.2a/2.5a/4a) channel 3 buck regulator (1.2a) oscillator int vreg 100ma q1 q2 l1 1.5h 1.5h 6.8h 10h l2 5v reg sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 vreg l3 bst3 sw3 fb3 pgnd3 l4 bst4 sw4 fb4 pgnd4 vreg pvin1 comp1 en1 pvin2 comp2 en2 pvin3 ss34 comp3 en3 pvin4 comp4 en4 c2 10f 4.7nf 10k 100k 600k 31.6k 2.7nf 6.81k 2.7nf 6.81k c1 1.0f c4 100f c3 0.1f c5 10f c6 0.1f c8 10f c9 0.1f c10 22f c11 10f c12 0.1f c13 22f 12v vout1 vout3 1.2v/8a 1.5v/1.2a 3.3v/1.2a vout4 22k 22k 5v reg exposed pad ss12 c0 1.0f vdd watchdog and reset vth wdi ADP5053 channel 1 buck regulator (1.2a/2.5a/4a) channel 4 buck regulator (1.2a) c18 100f vreg mr rsto 4.99k 10k 10k 51k 10k 8.87k 31.6k 10.2k 10.2k si7232dn (16.4m ) 11636-060 figure 54. typical channel 1/channel 2 parallel out put application, 600 khz switching frequency, adjus table output model
ADP5053 preliminary technical data rev. prb | page 38 of 41 factory programmable options table 16 to table 30 list the options that can be p rogrammed into the ADP5053 when it is ordered from analog devices. for a list of the default options, see table 31. to ord er a device with options other than the default options, contact you r local analog devices sales or distribution representative . table 16. output voltage options for channel 1 (fix ed output options: 0.85 v to 1.6 v in 25 mv increments ) option description option 0 0.8 v adjustable output (default) option 1 0.85 v fixed output option 2 0.875 v fixed output option 30 1.575 v fixed output option 31 1.6 v fixed output table 17. output voltage options for channel 2 (fix ed output options: 3.3 v to 5.0 v in 300 mv/200 mv increments) option description option 0 0.8 v adjustable output (default) option 1 3.3 v fixed output option 2 3.6 v fixed output option 3 3.9 v fixed output option 4 4.2 v fixed output option 5 4.5 v fixed output option 6 4.8 v fixed output option 7 5.0 v fixed output table 18. output voltage options for channel 3 (fix ed output options: 1.2 v to 1.8 v in 100 mv increments ) option description option 0 0.8 v adjustable output (default) option 1 1.2 v fixed output option 2 1.3 v fixed output option 3 1.4 v fixed output option 4 1.5 v fixed output option 5 1.6 v fixed output option 6 1.7 v fixed output option 7 1.8 v fixed output table 19. output voltage options for channel 4 (fix ed output options: 2.5 v to 5.5 v in 100 mv increments ) option description option 0 0.8 v adjustable output (default) option 1 2.5 v fixed output option 2 2.6 v fixed output option 30 5.4 v fixed output option 31 5.5 v fixed output table 20. pwrgd pin (pin 20) output options option description option 0 no monitoring of any channel option 1 monitor channel 1 output (default) option 2 monitor channel 2 output option 3 monitor channel 1 and channel 2 outputs option 4 monitor channel 3 output option 5 monitor channel 1 and channel 3 outputs option 6 monitor channel 2 and channel 3 outputs option 7 monitor channel 1, channel 2, and channel 3 outputs option 8 monitor channel 4 output option 9 monitor channel 1 and channel 4 outputs option 10 monitor channel 2 and channel 4 outputs option 11 monitor channel 1, channel 2, and channel 4 outputs option 12 monitor channel 3 and channel 4 outputs option 13 monitor channel 1, channel 3, and channel 4 outputs option 14 monitor channel 2, channel 3, and channel 4 outputs option 15 monitor channel 1, channel 2, channel 3, and channel 4 outputs table 21. output discharge function options option description option 0 output discharge function disabled for all four buck regulators option 1 output discharge function enabled for all four buck regulators (default) table 22. switching frequency options for channel 1 option description option 0 1 switching frequency set by the rt pin (default) option 1 ? switching frequency set by the rt pin table 23. switching frequency options for channel 3 option description option 0 1 switching frequency set by the rt pin (default) option 1 ? switching frequency set by the rt pin table 24. sync/mode pin (pin 43) function options option description option 0 forced pwm/automatic pwm/psm mode setting with the ability to synchronize to an external cloc k option 1 generate a clock signal equal to the maste r frequency set by the rt pin
preliminary technical data ADP5053 rev. prb | page 39 of 41 table 25. hiccup protection options for the four bu ck regulators option description option 0 hiccup protection enabled for overcurrent events (default) option 1 hiccup protection disabled; frequency fold back protection only for overcurrent events table 26. short-circuit latch-off function options for the four buck regulators option description option 0 latchoff function disabled for output sho rt circuit events (default) option 1 latchoff function enabled for output shor t circuit events table 27. overvoltage latch-off function options fo r the four buck regulators option description option 0 latchoff function disabled for output overvoltage events (default) option 1 latchoff function enabled for output overvoltage events table 28. reset timeout period options option description option 0 1.4 ms option 1 28 ms option 2 200 ms (default) option 3 1.6 sec table 29. watchdog timeout period options option description option 0 6.3 ms option 1 102 ms option 2 1.6 sec (default) option 3 25.6 sec table 30. manual reset input mode options option description option 0 processor manual reset mode (default) option 1 power on/off switch mode factory default options table 31 lists the factory default options programm ed into the ADP5053 when the device is ordered (see the ordering guide ). to order the device with options other than the def ault options, contact your local analog devices sales or distribu tion representative. table 16 to table 30 list all avail able options for the device. table 31. factory default options option default value channel 1 output voltage 0.8 v adjustable output channel 2 output voltage 0.8 v adjustable output channel 3 output voltage 0.8 v adjustable output channel 4 output voltage 0.8 v adjustable output pwrgd pin (pin 20) output monitor channel 1 output output discharge function enabled for all four buck regulators switching frequency on channel 1 1 switching frequency set by the rt pin switching frequency on channel 3 ? switching frequency set by the rt pin sync/mode pin (pin 43) function forced pwm/automatic pwm/psm mode setting with the ability to synchronize to an external clock hiccup protection enabled for overcurrent events shortcircuit latchoff function disabled for output shortcircuit events overvoltage latchoff function disabled for output overvoltage events reset timeout period 200 ms watchdog timeout period 1.6 sec manual reset input mode processor manual reset mode
ADP5053 preliminary technical data rev. prb | page 40 of 41 outline dimensions 1 0.50 bsc bottom view top view pin 1 indicator 48 13 24 36 37 exposed pad p i n 1 i n d i c a t o r * 5.65 5.60 sq 5.55 0.50 0.40 0.30 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.20 04-26-2013-c 7.10 7.00 sq 6.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min * compliant to jedec standards mo-220-wkkd-2 with the exception of the exposed pad dimension. figure 55. 48-lead lead frame chip scale package [l fcsp_wq] 7 mm 7 mm body, very very thin quad (cp-48-13) dimensions shown in millimeters ordering guide model 1 temperature range package description package opti on 2 ADP5053acpzr7 ?40c to +125c 48lead lead frame c hip scale package [lfcsp_wq] cp4813 ADP5053evalz evaluation board 1 z = rohs compliant part. 2 table 31 lists the factory default options for the device. for a list of factory programmable options , see the factory programmable options section. to order a device with options other than the default options, contac t your local analog devices sales or distribution r epresentative.
preliminary technical data ADP5053 rev. prb | page 41 of 41 notes ? 2013 analog devices, inc. all rights reserved . trademarks and registered trademarks are the property of their re spective owners. pr1163609/13 (prb)

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